There is a continued need in the semiconductor industry to decrease the size of the IC devices. At the same time there is a demand for reducing power consumption while increasing the overall speed of operations. The needs for low power consumption along with reduced device sizes and increased operational speed pose a particular challenge in design of today's comparators.
The vector and accumulator comparators are usually part of the data paths of digital signal processor (DSP) chips and other similar devices. Comparator operations are directly controlled by the DSP after instructions are issued. Data operation in the comparator macro is conducted at DSP speed, usually in one clock cycle. Therefore, a low power and high speed DSP require low power and high speed data macros. The advent of super scale architecture for vector data path and accumulator data path. A 16-bit vector data path pipe consists of vector multiplier(s), vector adder(s), vector logic, vector shifter(s) and vector comparator macros. The 40 bit accumulator data-path pipe, by comparison, consists of saturating adder(s), accumulator logic and accumulator comparator macros. All data macros receive data simultaneously through the transition register barrier. Therefore, the need of low power and high speed comparators at different points in the data paths pose a challenge.
In addition, power and silicon areas for the comparator macro becomes significantly larger when the comparator goes from that of a simple integer non-signed use to floating point signed number use and non-signed use. An improved comparator should have the capability of doing both signed and non-signed numbers with the sign control signal telling the comparator macro if the data is signed or non-signed (i.e. The instruction is integer or floating point arithmetic). There is therefore a need for such an improved comparator design that can combine the high speed and low power demands of present semiconductor devices while supporting the decreased overall device sizes.